Information processing apparatus and method for controlling the same

ABSTRACT

There is provided an information processing apparatus in which a plurality of modules including at least a first module and a second module is connected in a ring shape. The first module includes a first transmission unit configured to transmit predetermined data. The second module adjacent to the first module includes a second reception unit configured to receive the predetermined data transmitted by the first transmission unit, and a second transmission unit configured to transmit first attribute data including identification information for identifying a module when the predetermined data has not been received within a first predetermined time period.

BACKGROUND OF THE INVENTION Field of the Invention

The present invention relates to an information processing apparatus anda method for controlling the information processing apparatus.

Description of the Related Art

There has conventionally been proposed a system in which a plurality ofdata processing units is connected in a ring shape via a data bus. Datais transmitted in one direction of the ring-shaped data bus to enabledata exchange between a plurality of the data processing units (refer toJapanese Patent Application Laid-Open No. 2010-245953).

In a conventional self-diagnostic method for a bus connected in a ringshape (self-diagnosis method for a data transmission line), a normalcondition (OK) is determined when data transmitted from a main chipreturns to the main chip via the ring-shaped bus, and an abnormalcondition (NG) is determined when the data does not return to the mainchip. However, the conventional method has an issue that, when anabnormal condition is determined, it is not possible to determine wherein the ring-shaped bus a failure has occurred, i.e., to determine thefailure location. The conventional method consumes time and requiresmuch cost in failure location analysis, and therefore easymaintainability is not obtained.

SUMMARY OF THE INVENTION

The present invention is directed to providing a mechanism for making itpossible to identify a failure location even if a failure occurs in aring-shaped bus.

There is provided an information processing apparatus in which aplurality of modules including at least a first module and a secondmodule is connected in a ring shape. The first module includes a firsttransmission unit configured to transmit predetermined data. The secondmodule adjacent to the first module includes a second reception unitconfigured to receive the predetermined data transmitted by the firsttransmission unit, and a second transmission unit configured to transmitfirst attribute data including identification information foridentifying a module when the predetermined data has not been receivedwithin a first predetermined time period.

Further features of the present invention will become apparent from thefollowing description of exemplary embodiments with reference to theattached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a configuration of an imageprocessing apparatus according to the present exemplary embodiment.

FIG. 2 is a block diagram illustrating details of a transmission unit ina main chip.

FIG. 3 is a block diagram illustrating details of a reception unit in asub chip.

FIG. 4 is a block diagram illustrating details of a transmission unit ina sub chip according to a first exemplary embodiment.

FIG. 5 is a block diagram illustrating details of a reception unit inthe main chip.

FIGS. 6A and 6B illustrate a packet configuration according to thepresent exemplary embodiment.

FIGS. 7A and 7B are flowcharts illustrating control processing of thesub chip according to the first exemplary embodiment.

FIG. 8 is a flowchart illustrating control processing of the main chipaccording to the first exemplary embodiment.

FIGS. 9A and 9B illustrate input and output waveforms of each chip whenan NG packet is generated in a ring bus self-diagnostic operation.

FIGS. 10A and 10B illustrate input and output waveforms of each chipwhen an NG packet is not generated in the ring bus self-diagnosticoperation.

FIG. 11 illustrates details of the transmission unit in the sub chipaccording to a second exemplary embodiment.

FIG. 12 is a flowchart illustrating control processing of the sub chipaccording to the second exemplary embodiment.

FIG. 13 is a flowchart illustrating control processing of the main chipaccording to the second exemplary embodiment.

DESCRIPTION OF THE EMBODIMENTS

Exemplary embodiments of the present invention will be described belowwith reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating a configuration of an imageprocessing apparatus 100 to which an information processing apparatusaccording to a first exemplary embodiment of the present invention isapplicable.

The image processing apparatus 100 according to the present exemplaryembodiment includes a main chip 110 and sub chips 120, 130, and 140connected in a ring shape by ring buses 191, 192, 193, and 194, andconfigured to perform data transmission in this order. The number of subchips connected by the ring-shaped bus is not limited to three and maybe one or more. More specifically, the main chip and one or more subchips need to be connected in the ring-shaped bus to enable sequentialdata transmission.

Data is transmitted between the above-described chips in predeterminedunits, i.e., in units of a packet. The configuration of a packet will bedescribed below with reference to FIG. 6A.

FIG. 6A illustrates a packet configuration according to the firstexemplary embodiment.

According to the first exemplary embodiment, each packet is configuredas illustrated in FIG. 6A. More specifically, each packet includes achip identifier (ID) area, a packet type area, a packet size area, and adata area.

The chip ID area stores chip ID information that specifies thedestination of the packet. The packet type area stores the packet typewhich explicitly indicates whether the packet is a packet (OK packet/NGpacket) to be used in the ring bus self-diagnostic operation or aregular packet. The ring bus self-diagnostic operation refers to anoperation in which the image processing apparatus 100 performsself-diagnosis on the data transmission line in the ring-shaped bus todetect a failure location in the ring-shaped bus (described in detailbelow).

The packet type is “0” for a regular packet, “1” for an OK packet(packet having the OK attribute), and “2” for an NG packet (packethaving the NG attribute). The packet size area stores the packet sizewhich indicates the size of the packet. The data area stores the data tobe transmitted by the packet. When the packet type stored in the packettype area in the ring bus self-diagnostic operation (described below) isNG, debugging information is stored in the data area in an NG packet.

Description of FIG. 1 will be resumed.

Each of reception units 113, 123, 133, and 143 of the chips 110, 120,130, and 140 refers to the chip ID of the packet. When the destinationof the packet is itself, the reception unit of the chip transmits thepacket to the internal block 112, 122, 132, or 142. On the other hand,when the destination of the packet is not itself, the chip transmits thepacket as it is to the next (downstream) chip via the transmission unit114, 124, 134, or 144 of the chip.

When any one of the chips 110, 120, 130, and 140 has data to betransmitted, the chip generates a packet containing the data and addsdestination information (chip ID) to the packet to transmit data to anydesired chip. More specifically, the chips 110, 120, 130, and 140 areconfigured to perform data transmission and reception with each othervia the ring-shaped bus.

The main chip 110 receives a copying, printing, and reading command fromthe user via a user interface (UI) unit 170 or outputs a message to theuser. The main chip 110 is also connected with a network 180 to receiveprint data from other host computers connected to the network.

The sub chip 120 performs, via the printing image processing unit 122,image processing (color conversion and binarization and the like,)suitable for a printing unit 150 on the image data transmitted from themain chip 110, and transmits the processed image data to the printingunit 150. Based on the image data, the printing unit 150 forms an imageon a paper sheet, for example, by using the electrophotographic method.

The sub chip 130 performs, via the editing image processing unit 132,processing (rotation and reduction) on image data transmitted from themain chip 110, and transmits the processed image data to the main chip110.

The sub chip 140 performs, via the read image processing unit 142, imageprocessing for reading (color correction and filter processing) on imagedata transmitted from a reading unit 160, and transmits the processedimage data to the main chip 110. The reading unit 160 optically scans animage such as a document and converts the image into digital data.

The image data transmitted from the sub chips 130 and 140 is stored in astorage unit 190 via the main chip 110.

In the image processing apparatus 100 configured as described above, themain chip 110 totally controls each component to achieve the copy,printing, and reading functions.

The main control unit 112 of the main chip 110 implements aconfiguration for achieving the ring bus self-diagnostic operation inthe main chip 110 illustrated in the flowchart (described below). Themain control unit 112 implements this configuration, for example, as aprogram and performs control illustrated in the flowcharts (describedbelow).

The transmission unit and reception unit of each chip will be describedbelow according to the data transmission sequence.

First, the transmission unit 114 in the main chip 110 will be describedbelow.

FIG. 2 is a block diagram illustrating details of the transmission unit114 in the main chip 110. Although the present exemplary embodimentdescribed below is based on a high-speed serial interface used forconnection between chips, the configuration is not limited thereto.

In the transmission unit 114 illustrated in FIG. 2, a packet generationunit 220 is used to generate an OK packet. The OK packet is a packetoutput from the main chip 110 in the ring bus self-diagnostic operationwhich characterizes the present invention. The OK packet generation unit220 sets the packet type “1” which indicates that the packet is an OKpacket, to the packet type area of the OK packet. The OK packet isdistinguished from an NG packet with this packet type. The OK packetgeneration unit 220 also sets the chip ID “0” of the main chip 110 tothe chip ID area of the OK packet so that the OK packet returns to themain chip 110.

A selector 230 selects either the packet from the main control unit 112or the OK packet and outputs the selected packet. A transmission PHY 210converts the packet selected by the selector 230 into serial data andoutputs the serial data at high frequency. According to the presentexemplary embodiment, a packet is input to the transmission PHY 210 inunits of 8 bits. An 8B-10B coding unit 215 in the transmission PHY 210converts 8 bits into bits based on a predetermined rule. Aparallel-to-serial conversion unit 213 converts the 10-bit dataconverted by the 8B-10B coding unit 215 into serial data. A differentialdriver 211 differentially outputs the serial data converted by theparallel-to-serial conversion unit 213. The 8B-10B coding unit 215guarantees that the High and Low levels of the serial data are uniformand that one level does not last for a prolonged time period. Thisenables a Clock Data Recovery (CDR) 312 in a reception PHY 310 of thereception unit 123 illustrated in FIG. 3 (described below) to restore aclock.

The differential signal output from the transmission unit 114 within themain chip 110 is received by the reception unit 123 within the sub chip120.

The reception unit 123 within the sub chip 120 will be described below.

FIG. 3 is a block diagram illustrating details of the reception unit 123within the sub chip 120. The reception unit 123 has a configurationsimilar to the reception unit 133 within the sub chip 130 and thereception unit 143 within the sub chip 140.

The reception PHY 310 receives a differential signal transmitted fromthe transmission unit of the upstream chip and restores the packet. Adifferential receiver 311 within the reception PHY 310 receives thedifferential signal. The CDR 312 restores the clock from thedifferential signal received by the differential receiver 311 andoutputs serial data to the serial-to-parallel conversion unit 313. Theserial-to-parallel conversion unit 313 converts the serial data outputfrom the CDR 312 and outputs parallel data to the elastic buffer 314.The parallel data passes through an elastic buffer 314 for absorbing thefrequency difference between the transmission unit 124 and the receptionunit 123, and is decoded from 10-bit data into 8-bit data by an 8B-10Bdecoding unit 315. As described above, the packet input to thetransmission PHY 210 in the transmission unit 114 of the main chip 110is restored as the output of the reception PHY 310 of the sub chip 120.

The PHY 310 constantly outputs an error status 370. Error statuselements (error elements) will be described below.

A “signal detection error” indicates that a differential receiver (forexample, the differential receiver 311) cannot detect the leveldifference of the differential signal, i.e., a failure in a differentialdriver (for example, the differential driver 211) or a disconnectionbetween chips (for example, a disconnection on the ring bus 191) isassumed. An “8B-10B decoding error” indicates that a signal train(symbols) other than the predetermined 10-bit data has been received. Itcan be thought that a transmission error has occurred because of a smallnoise margin of the differential signal line between the chips or noiseadded on a signal line.

An “elastic buffer overflow” indicates that the elastic buffer hasoverflowed because the transmission frequency of the transmission unitis excessively higher than the reception frequency of the receptionunit.

An “elastic buffer underflow” indicates that the elastic buffer hasunderflowed because the transmission frequency of the transmission unitis excessively lower than the reception frequency of the reception unit,resulting in an interruption of reception data.

For example, in a state where there is no error corresponding to theabove-described error elements, the error status 370 is information (forexample, a bit sequence “0000”) corresponding to a signal detectionerror: (not detected), an 8B-10B decoding error: 0 (not detected), anelastic buffer overflow: 0 (not detected), and an elastic bufferunderflow: 0 (not detected). In a state where there is only a signaldetection error, the error status 370 is information (for example, a bitsequence “1000”) corresponding to a signal detection error: 1(detected), an 8B-10B decoding error: 0 (not detected), an elasticbuffer overflow: 0 (not detected), and an elastic buffer underflow: 0(not detected).

The switch 350 switches the destination of the packet output from thereception PHY 310 between the printing image processing unit 122 and thetransmission unit 124 based on the chip ID of the packet. Morespecifically, when the chip ID of the packet is “1”, the switch 360selects the printing image processing unit 122 as the destination of thepacket. When the chip ID is not “1”, the switch 360 selects thetransmission unit 124 as the destination of the packet. At the time ofthe ring bus self-diagnostic operation, since the chip ID of both the OKand NG packets is “0”, the destination is the main chip 110 andtherefore the packet is transmitted to the transmission unit 124.

The transmission unit 124 within the sub chip 120 will be describedbelow.

FIG. 4 is a block diagram illustrating details of the transmission unit124 within the sub chip 120. The transmission unit 124 has aconfiguration similar to the transmission unit 134 within the sub chip130 and the transmission unit 144 within the sub chip 140.

The NG packet generation unit 420 is operated to generate an NG packet.The NG packet generation unit 420 generates the NG packet based on theerror status 370 output by the reception unit 123 and the chipidentification information output by a chip identification informationstorage unit 430. The NG packet generation unit 420 sets in the packettype area of the NG packet the packet type “2” which indicates that thepacket is the NG packet. The NG packet is distinguished from an OKpacket with this packet type.

An arbitration unit 450 performs arbitration to determine whether apacket is to be received from the reception unit 123 or from theprinting image processing unit 122. The selector 440 selects either apacket from the arbitration unit 450 or the NG packet and outputs theselected packet.

The transmission control unit 401 implements a configuration forperforming the ring bus self-diagnostic operation in the sub chipillustrated in the flowchart (described below). The transmission controlunit 401 implements this configuration, for example, as a program andperforms control illustrated in the flowcharts described below.

A transmission PHY 410 has a configuration similar to the transmissionPHY 210 illustrated in FIG. 2, therefore, redundant descriptions thereofwill be omitted.

The output from the transmission unit 124 within the sub chip 120 isreceived by the reception unit 133 within the sub chip 130. The outputfrom the transmission unit 134 within the sub chip 130 is received bythe reception unit 143 within the sub chip 140. The output from thetransmission unit 144 within the sub chip 140 is received by thereception unit 113 within the main chip 110.

Finally, the reception unit 113 within the main chip 110 will bedescribed below.

FIG. 5 is a block diagram illustrating details of the reception unit 113within the main chip 110.

A reception PHY 510 has a configuration similar to the reception PHY310, and redundant descriptions thereof will be omitted. An error status570 is transmitted to the main control unit 112.

A packet output from the reception PHY 510 is transmitted to the maincontrol unit 112. Both the OK and NG packets are stored in the testpacket storage unit 530.

The ring bus self-diagnostic operation in the above-describedconfiguration will be described below.

Processing illustrated in the following flowcharts is started when theimage processing apparatus 100 is supplied with power and a system startsignal (not illustrated) is transmitted to each chip (at a predeterminedtiming indicated by time t0 illustrated in FIGS. 9A, 9B, 10A, and 10B).The processing is not performed at the same time as regular operationssuch as the copy, print, and read operations. The ring busself-diagnostic operation is performed when the main chip 110 and thesub chips 120, 130, and 140 perform their own control processing. Forexample, the main chip 110 performs the ring bus self-diagnosticoperation by executing the control illustrated in FIG. 8. The sub chip120 performs the ring bus self-diagnostic operation by executing thecontrol illustrated in FIG. 7A. The sub chip 130 performs the ring busself-diagnostic operation by executing the control illustrated in FIG.7B. The sub chip 140 performs the ring bus self-diagnostic operation byexecuting control (not illustrated) similar to the control illustratedin FIG. 7B.

The ring bus self-diagnostic operation will be described below.

Input and output waveforms of the four chips when the NG packet isgenerated and when the NG packet is not generated in the ring busself-diagnostic operation will be described below with reference toFIGS. 9A, 9B, 10A, and 10B.

Input and output waveforms of the four chips when the NG packet isgenerated in the ring bus self-diagnostic operation is illustrated inFIG. 9A. A packet (NG packet) received by the main chip 110 isillustrated in FIG. 9B.

Input and output waveforms of the four chips when the NG packet is notgenerated in the ring bus self-diagnostic operation is illustrated inFIG. 10A. A packet (OK packet) received by the main chip 110 isillustrated in FIG. 10B.

Operations of the four chips will be described below with reference toFIGS. 7A, 7B, and 8.

[Control by Sub Chip 120]

FIG. 7A is a flowchart illustrating control processing of the sub chip120. Processing of this flowchart is performed under the control of thetransmission control unit 401 of the sub chip 120.

When the processing of this flowchart is started (at time t0 illustratedin FIGS. 9A, 9B, 10A, and 10B), in step S701, the transmission controlunit 401 determines whether a received packet is transmitted from thereception unit 123. When the transmission control unit 401 determinesthat a received packet has not been transmitted (NO in step S701), theprocessing proceeds to step S702. In step S702, the transmission controlunit 401 determines whether a time period Tw1 has elapsed from when thisprocessing has started. When the transmission control unit 401determines that the time period Tw1 has not elapsed (NO in step S702),the processing returns to step S701. More specifically, after startingthis processing, in steps S701 and S702, the transmission control unit401 waits (monitors the processing) for the time period Tw1 until areceived packet is transmitted from the reception unit 123. Thepredetermined time period Tw1 is preset to the sub chip 120 as asufficient wait time for the sub chip 120 to complete the reception ofthe OK or NG packet.

When the transmission control unit 401 determines that a received packethas not been transmitted from the reception unit 123 even after the timeperiod Tw1 has elapsed (NO in step S701 and YES in step S702), theprocessing proceeds to step S703. In step S703, the transmission controlunit 401 controls the NG packet generation unit 420 to generate the NGpacket including the error status 370 and the chip identificationinformation output from the chip identification information storage unit430. In this case, the transmission control unit 401 controls theselector 440 to constantly select the output of the NG packet generationunit 420. As a result, the sub chip 120 outputs an NG packet.

On the other hand, when the transmission control unit 401 determinesthat a received packet has been transmitted from the reception unit 123before the time period Tw1 has elapsed (YES in step S701), theprocessing proceeds to step S705. In step S705, the transmission controlunit 401 controls the transmission PHY 410 to output the received packetas it is. More specifically, in this case, the transmission control unit401 controls the selector 440 to select the output of the arbitrationunit 450 (received packet). As a result, the sub chip 120 outputs thereceived packet as it is.

[Control by Sub Chip 130]

FIG. 7B is a flowchart illustrating control processing of the sub chip130. Steps identical to those in FIG. 7A are assigned the same stepnumbers. Processing of this flowchart is performed under the control ofthe transmission control unit 401 of the sub chip 130.

The difference between the control by the sub chip 130 (FIG. 7B) and thecontrol by the sub chip 120 (FIG. 7A) is only the wait time in stepS712. More specifically, in step S712, the sub chip 130 waits for apacket reception for a time period “Tw1+α”, while in step S702, the subchip 120 waits for a packet reception for the time period “Tw1”. This isbecause, when the sub chip 120 outputs the NG packet at a time “t0+Tw1”,the sub chip 130 further requires a packet transmission time period (α)to detect the packet. The predetermined time period Tw1+α is previouslyset to the sub chip 130 as a sufficient wait time for the sub chip 130to complete the reception of the OK or NG packet.

The processing in step S705 executed after the transmission control unit401 determines that the received packet is present in step S701, isprocessing in common with the control by the sub chip 120.

[Control by Sub Chip 140]

Similarly, the control by the sub chip 140 differs from the control bythe sub chip 120 only in the wait time. Therefore, a flowchartillustrating the control by the sub chip 140 will be omitted. Since thesub chip 140 needs to wait for an additional time period a compared withthe sub chip 130 for the above-described reason, therefore, needs tomonitor packet reception for a time period Tw1+2α from time t0. Morespecifically, when the control is performed by the sub chip 140, “Tw1+α”in step S712 illustrated in FIG. 7B is replaced with “Tw1+2α”. Thepredetermined time period Tw1+2α is preset to the sub chip 140 as asufficient wait time for the sub chip 140 to complete the reception ofthe OK or NG packet.

More specifically, when a packet is received from the bus within a waittime starting from when power is turned ON which is predetermined foreach sub chip, each sub chip outputs the received packet to the bus. Onthe other hand, when no packet is received from the bus within the waittime, each sub chip generates the NG packet and outputs it to the bus.

[Control by Main Chip 110]

FIG. 8 is a flowchart illustrating control processing of the main chip110. Processing of this flowchart is performed under the control of themain control unit 112 of the main chip 110.

When processing of this flowchart is started (at time t0 illustrated inFIGS. 9A, 9B, 10A, and 10B), in step S801, the main control unit 112controls the OK packet generation unit 220 to generate and output the OKpacket. In this case, the main control unit 112 controls the selector230 to constantly select the output of the OK packet generation unit220. As a result, the main chip 110 outputs one OK packet.

In step S802, the main control unit 112 waits for a predetermined timeperiod Tw2. The predetermined time period Tw2 is preset to the maincontrol unit 112 as a sufficient wait time for the main control unit 112to complete the reception of the OK or NG packet when returning thepacket to the main chip 110. When the reception unit 113 of the mainchip 110 receives a packet during the wait time in step S802, thereception unit 113 stores the packet in a test packet storage unit 530.

After waiting for the time period Tw2 (at time t2), in step S803, themain control unit 112 checks the test packet storage unit 530 todetermine whether a packet has been received in the above-mentioned waittime. When the transmission control unit 401 determines that no packethas been received (NO in step S803), the processing proceeds to stepS804.

In step S804, the main control unit 112 determines that a failure hasoccurred in the path from the transmission unit 144 of the sub chip 140to the reception unit 113 of the main chip 110. The main control unit112 presumes the error factor based on the error status 570 output bythe reception unit 113. The error factor is described above withreference to FIG. 3. For example, in the case of signal detection error:1 (detected), the main control unit 112 presumes a failure in thedifferential driver 411 of the sub chip 140 or a disconnection of thering bus 194.

In step S808, the main control unit 112 displays the determinationresult in step S804 and the error factor presumption result on the UIunit 170, and the processing exits this flowchart.

On the other hand, when the transmission control unit 401 determinesthat a packet has been received (YES in step S803), the processingproceeds to step S805.

In step S805, the main control unit 112 checks the packet (test packet)stored in the test packet storage unit 530 to determine whether the testpacket is the NG packet. When the transmission control unit 401determines that the test packet is the NG packet (YES in step S805), theprocessing proceeds to step S806.

In step S806, the main control unit 112 determines that a failure hasoccurred in the ring bus transmission path and presumes the failurelocation and error factor based on the NG packet generation chipinformation and the error status information included in the received NGpacket (status information of the NG packet generation source sub chip).A specific example of the presumption of the failure location and errorfactor will be described below.

For example, a disconnection failure which occurs in the ring bus 192will be described below. Input and output waveforms of the four chips inthis case are illustrated in FIG. 9A. In this case, the sub chip 130does not receive a packet and therefore transmits the NG packet (timet1) under the control of the sub chip illustrated in FIG. 7B. Thefollowing sub chip 140 transmits the received NG packet to the ring busin the subsequent stage under the control of the above-described subchip. As a result, the NG packet is stored in the test packet storageunit 530 of the main chip 110. An example of the NG packet stored in thetest packet storage unit 530 is illustrated in FIG. 9B. The main controlunit 112 detects that the packet type is “2 (NG)” and that the NG packethas been generated by the sub chip 130 based on the NG packet generationsource chip information (“2” in the example illustrated in FIG. 9B). Themain control unit 112 further detects that a signal detection error hasoccurred based on the error status information “signal detection error:1 (detected)”. Then, the main control unit 112 presumes a failure in thedifferential driver 411 of the sub chip 120 or a disconnection of thering bus 192 as an error factor.

In step S809, the main control unit 112 displays the determinationresult in step S806 and the presumption result on the UI unit 170, andthe processing exits this flowchart.

On the other hand, when the transmission control unit 401 determinesthat the test packet stored in the test packet storage unit 530 is notthe NG packet (NO in step S805), the main control unit 112 determinesthe test packet as an OK packet. Then, the processing proceeds to stepS807.

In step S807, the main control unit 112 determines that no failure hasoccurred in the ring bus transmission path. A case where no failure hasoccurred will be described below with reference to a specific example.

If the main control unit 112 receives the OK packet, the OK packetshould have passed through the sub chips 120, 130, and 140, asillustrated in FIG. 10A. Therefore, the main control unit 112 determinesthat no failure has occurred in the ring bus transmission path. The OKpacket stored in the test packet storage unit 530 is illustrated in FIG.10B.

After the main control unit 112 performs the processing in step S807,the processing exits this flowchart.

More specifically, when power is turned ON, the main chip 110 outputsthe OK packet to the bus. Then, based on whether data has been receivedfrom the bus within the time period Tw2, and based on the NG packetgeneration source chip ID and the status information included in the NGpacket received from the bus within the time period Tw2, the main chip110 determines the failure location in the ring-shaped bus and presumesthe failure factor.

As described above, even if a failure occurs in the ring-shaped bus, theimage processing apparatus 100 according to the first exemplaryembodiment can automatically detect the failure location andautonomously presume the failure factor at the timing that power isturned ON. As a result, the maintainability of the image processingapparatus 100 can be improved.

The execution timing of the ring bus self-diagnostic operation is notlimited to the timing that power of the image processing apparatus 100is turned ON. The ring bus self-diagnostic operation can also beexecuted based on an operation performed on the UI unit 170 and aninstruction from an external apparatus such as a personal computer (PC)connected via the network 180. In this case, the determination andpresumption results are displayed on the instruction source (such as theUI unit 170 and PC). This configuration enables detecting the failurelocation and error factor based on a user instruction also in a casewhere a failure occurs in the ring-shaped bus. As a result, themaintainability of the image processing apparatus 100 can be improved.

Also after the processing in step S807, i.e., also in a case where themain control unit 112 determines that no failure has occurred in thering bus transmission path, the main control unit 112 may output thedetermination result in step S807 to the UI unit 170. For example, whenthe ring bus self-diagnostic operation is instructed from the UI unit170, the determination result in step S807 may also be displayed on theUI unit 170. When the ring bus self-diagnostic operation is instructedfrom the PC via the network 180, the determination result in step S804,S806, or S807 may be notified to the instruction source (PC) via thenetwork 180.

A second exemplary embodiment will be described below. The firstexemplary embodiment has been described with respect to a configurationin which the transmission unit of each sub chip includes the chipidentification information storage unit 430 and generates an NG packetwith which the NG packet generation source chip can be identified, basedon the chip identification information output by the chip identificationinformation storage unit 430. The second exemplary embodiment will bedescribed below with respect to the ring bus self-diagnostic operationwhich enables identifying the NG packet generation source chip even inthe image processing apparatus 100 in which a sub chip including thetransmission unit provided with no chip identification informationstorage unit 430 is connected to the main chip 110 via the ring-shapedbus. The processing for presuming the failure factor based on the errorstatuses 370 and 570 is similar to the first exemplary embodiment, anddescriptions thereof will be omitted.

FIG. 11 is a block diagram illustrating details of the transmission unit124 in the sub chip 120 according to the second exemplary embodiment.The transmission unit 124 has a configuration similar to thetransmission unit 134 in the sub chip 130 and the transmission unit 144in the sub chip 140. The transmission unit 124 according to the secondexemplary embodiment illustrated in FIG. 11 is different from thetransmission unit 124 according to the first exemplary embodimentillustrated in FIG. 4 in that it does not include the chipidentification information storage unit 430 and but includes an NGpacket change unit 1160. The NG packet generation unit 420 according tothe second exemplary embodiment is different from the NG packetgeneration unit 420 according to the first exemplary embodiment in thatit generates an NG packet having the packet passage number “0” (NG_0packet). The packet passage number is stored in the passage number areaof a test packet as illustrated in FIG. 6B (described below). A packethaving the passage number area “n” is referred to as an “NG_n packet”.

When an NG packet is input as a received packet, the NG packet changeunit 1160 increments the packet passage number by one. When a packetother than the NG packet is input, the NG packet change unit 1160outputs the packet as it is.

A test packet configuration according to the second exemplary embodimentwill be described below with reference to FIG. 6B.

FIG. 6B illustrates a test packet configuration according to the secondexemplary embodiment.

As illustrated in FIG. 6B, the test packet according to the secondexemplary embodiment has the passage number area for storing informationindicating the passage number of the packet.

Similar to the ring bus self-diagnostic operation according to the firstexemplary embodiment, the ring bus self-diagnostic operation accordingto the second exemplary embodiment is performed when the main chip 110and the sub chips 120, 130, and 140 perform their own controlprocessing. The ring bus self-diagnostic operation according to thesecond exemplary embodiment is implemented when the main chip 110performs control illustrated in FIG. 13, the sub chip 120 performscontrol illustrated in FIG. 12, and the sub chips 130 and 140 performcontrol (not illustrated) similar to the control illustrated in FIG. 12.

The ring bus self-diagnostic operation according to the second exemplaryembodiment will be described below.

[Control by Sub Chip 120]

FIG. 12 is a flowchart illustrating control processing of the sub chip120 according to the second exemplary embodiment as an example.Processing of this flowchart is performed under the control of thetransmission control unit 401 of the sub chip 120.

Processing in steps S1201 and S1202 is similar to the processing insteps S701 and S702 illustrated in FIGS. 7A and 7B and redundantdescriptions thereof will be omitted. However, when the transmissioncontrol unit 401 determines that a received packet has not yet beentransmitted from the reception unit 123 after the time period Tw1 haselapsed (NO in step S1201 and YES in step S1202), the processingproceeds to step S1203. In step S1203, the transmission control unit 401controls the NG packet generation unit 420 to generate an NG_0 packetincluding the error status 370. In this case, the transmission controlunit 401 controls the selector 440 to constantly select the output of NGpacket generation unit 420. As a result, the sub chip 120 outputs theNG_0 packet.

When the transmission control unit 401 determines that a received packethas been transmitted from the reception unit 123 before the time periodTw1 has elapsed (YES in step S1201), the processing proceeds to stepS1204.

In step S1204, the transmission control unit 401 checks the packet typeof the above-described received packet to determine whether the receivedpacket is an NG_n packet. When the transmission control unit 401determines that the received packet is the NG_n packet (YES in stepS1204), the processing proceeds to step S1205.

In step S1205, the transmission control unit 401 controls the NG packetchange unit 1160 to increment the value in the passage number area ofthe packet by one. As a result, the sub chip 120 outputs an NG_(n+1)packet.

On the other hand, when the transmission control unit 401 determinesthat the received packet is not the NG_n packet (NO in step S1204), theprocessing proceeds to step S1206. Processing in step S1206 is similarto the processing in step S705 illustrated in FIG. 7, and redundantdescriptions thereof will be omitted.

[Control by Sub Chips 130 and 140]

Also according to the second exemplary embodiment, the control by thesub chips 130 and 140 is different from the control by the sub chip 120only in the wait time. Therefore, a flowchart illustrating the controlby the sub chips 130 and 140 will be omitted. Since the sub chip 130needs to additionally wait for the sub chip 120 for a time period a forthe reason given in the first exemplary embodiment, the sub chip 130needs to monitor packet reception for a time period Tw1+α from time t0.Since the sub chip 140 needs to additionally wait for the sub chip 130for another time period a for the reason given in the first exemplaryembodiment, the sub chip 140 needs to monitor packet reception for atime period Tw1+2α from time t0. More specifically, when performing thecontrol by the sub chip 130, “Tw1” in step 51202 illustrated in FIG. 12is replaced with “Tw1+α”. Further, when performing the control by thesub chip 140, “Tw1” in step S1202 illustrated in FIG. 12 is replacedwith “Tw1+2α”.

[Control by Main Chip 110]

FIG. 13 is a flowchart illustrating control processing of the main chip110 according to the second exemplary embodiment. Processing of thisflowchart is performed under the control of the main control unit 112 ofthe main chip 110.

Processing in steps S1301 to S1304 is similar to the processing in stepS801 to S804 illustrated in FIG. 8, and redundant descriptions thereofwill be omitted. However, when the main control unit 112 determines thata packet is received in the wait time in step S1302 (YES in step S1303),the processing proceeds to step S1305.

In step S1305, the main control unit 112 checks the packet (test packet)stored in the test packet storage unit 530 to determine whether the testpacket is an NG_0 packet. When the main control unit 112 determines thatthe test packet is an NG_0 packet (YES in step S1305), the processingproceeds to step S1306.

In step S1306, since the received NG_0 packet indicates that the justpreceding sub chip 140 has generated the NG_0 packet, the main controlunit 112 determines that a failure has occurred in the path from thetransmission unit 134 of the sub chip 130 (sub chip preceding twostages) to the reception unit 143 of the sub chip 140, and presumes thefailure location and error factor based on the error status informationincluded in the received NG_0 packet.

On the other hand, when the main control unit 112 determines that thetest packet is not the NG_0 packet (NO in step S1305), the processingproceeds to step S1307.

In step S1307, the main control unit 112 determines whether the testpacket is an NG_1 packet. When the main control unit 112 determines thatthe test packet is the NG_1 packet (YES in step S1307), the processingproceeds to step S1308.

In step S1308, since the received NG_1 packet indicates that thepreceding sub chip 130 (sub chip preceding by two stages) has generatedthe NG_0 packet, the main control unit 112 determines that a failure hasoccurred in the path from the transmission unit 124 of the sub chip 120(sub chip preceding by three stages) to the reception unit 133 of thesub chip 130, and presumes the failure location and factor based on theerror status information included in the received NG_1 packet.

On the other hand, when the main control unit 112 determines that thetest packet is not the NG_1 packet (NO in step S1307), the processingproceeds to step S1309.

In step S1309, the main control unit 112 determines whether the testpacket is an NG_2 packet. When the main control unit 112 determines thatthe test packet is the NG_2 packet (YES in step S1309), the processingproceeds to step S1310.

In step S1310, since the received NG_2 packet indicates that thepreceding sub chip 120 (sub chip preceding by three stages) generatedthe NG_0 packet, the main control unit 112 determines that a failure hasoccurred in the path from the transmission unit 114 of the main chip 110to the reception unit 123 of the sub chip 120, and presumes the failurelocation and error factor based on the error status information includedin the received NG_2 packet.

On the other hand, when the main control unit 112 determines that thetest packet is not the NG_2 packet (NO in step S1309), the processingproceeds to step S1311.

In step S1311, the main control unit 112 determines that no failure hasoccurred in the ring bus transmission path, and the processing exitsthis flowchart.

After the processing in step S1304, S1306, S1308, or S1310 is performed,in steps S1312, the main control unit 112 displays the determination andpresumption results in step S1304, S1306, S1308, or S1310 on the UI unit170, and the processing exits this flowchart.

As described above, it is possible, if a failure occurs in thering-shaped bus, to detect the failure location and presume the errorfactor even in the image processing apparatus 100 in which a sub chipincluding the transmission unit provided with no chip identificationinformation storage unit 430 according to the second exemplaryembodiment is connected to the main chip 110 via the ring-shaped bus.

In the case of the control by the sub chip illustrated in the FIG. 12,in step 51205, the transmission control unit 401 controls the NG packetchange unit 1160 to increment the value in the passage number area(passage number) of the packet by one. However, the method for changingthe passage number performed by the sub chip having received the NGpacket is not limited to “increment by one” as described above. Themethod for changing the passage number is not limited to a particularconfiguration as long as the passage number generated with apredetermined initial value (not limited to 0) is changed based on apredetermined rule when the NG packet is output to the bus. For example,the passage number may be changed in such a way that the initial valueof the passage number when generating the NG packet is set to “100”, andthe passage number is decremented by one by the sub chip through whichthe NG packet passes.

Further, the passage number may be changed in such a way that thepassage number area is provided also in the OK packet, and thetransmission unit 124 of each sub chip changes the passage number of theOK packet before transmitting the OK packet.

According to each of the exemplary embodiments, the NG_packet includesinformation (identification information) for identifying the NG packetgeneration source sub chip to identify the failure location in thering-shaped bus. According to the first exemplary embodiment, theNG_packet includes the ID (chip ID) specific to the NG packet generationsource. According to the second exemplary embodiment, the NG_packetincludes the passage number and the NG packet generation source sub chipis identified by using the passage number, so that the failure locationin the ring-shaped bus is identified. However, the identificationinformation included in the NG packet is not limited to the chip ID andpassage number and may be other information as long as the NG packetgeneration source sub chip can be identified.

In each of the exemplary embodiments, the present invention is appliedto an image processing apparatus. However, the present invention isapplicable to any apparatus as long as the apparatus has a configurationin which a main module (such as the main chip 110) and at least one submodule (such as the sub chips 120 to 140) are connected in a ring shapeby a ring bus. For example, the present invention is applicable also tovarious types of information processing apparatuses such as householdappliances.

As illustrated above, according to the present invention, it is possibleto identify the failure location and error factor even if a failureoccurs in a ring-shaped bus. As a result, it becomes possible to reducethe cost of failure location analysis and improve the maintainability ofthe apparatus.

Other Embodiments

Embodiment(s) of the present invention can also be realized by acomputer of a system or apparatus that reads out and executes computerexecutable instructions (e.g., one or more programs) recorded on astorage medium (which may also be referred to more fully as a‘non-transitory computer-readable storage medium’) to perform thefunctions of one or more of the above-described embodiment(s) and/orthat includes one or more circuits (e.g., application specificintegrated circuit (ASIC)) for performing the functions of one or moreof the above-described embodiment(s), and by a method performed by thecomputer of the system or apparatus by, for example, reading out andexecuting the computer executable instructions from the storage mediumto perform the functions of one or more of the above-describedembodiment(s) and/or controlling the one or more circuits to perform thefunctions of one or more of the above-described embodiment(s). Thecomputer may comprise one or more processors (e.g., central processingunit (CPU), micro processing unit (MPU)) and may include a network ofseparate computers or separate processors to read out and execute thecomputer executable instructions. The computer executable instructionsmay be provided to the computer, for example, from a network or thestorage medium. The storage medium may include, for example, one or moreof a hard disk, a random-access memory (RAM), a read only memory (ROM),a storage of distributed computing systems, an optical disk (such as acompact disc (CD), digital versatile disc (DVD), or Blu-ray Disc (BD)™),a flash memory device, a memory card, and the like.

While the present invention has been described with reference toexemplary embodiments, it is to be understood that the invention is notlimited to the disclosed exemplary embodiments. The scope of thefollowing claims is to be accorded the broadest interpretation so as toencompass all such modifications and equivalent structures andfunctions.

This application claims the benefit of Japanese Patent Application No.2016-151027, filed Aug. 1, 2016, which is hereby incorporated byreference herein in its entirety.

What is claimed is:
 1. An information processing apparatus, comprising:a first processing unit including a first transmitter configured totransmit first data on a basis of powering the information processingapparatus and a first receiver configured to receive data transmittedfrom a second processing unit; the second processing unit including asecond receiver configured to receive the first data transmitted by thefirst transmitter and a second transmitter configured to transmit thefirst data transmitted from the first transmitter and second data to thefirst receiver; wherein the second data is data which is to betransmitted in a situation that the second receiver has not received thefirst data transmitted from the first transmitter since the informationprocessing apparatus was powered; and wherein, based on whether or notthe first receiver received the first data transmitted by the secondtransmitter and whether or not the first receiver received the seconddata transmitted by the second transmitter, the first processing unitidentifies failure location on a transmission path of the first data andthe data, wherein the first processing unit and the second processingunit are connected in a ring bus.
 2. The information processingapparatus according to claim 1, wherein, based on data received by thereceiver before a lapse of a predetermined time period sincetransmission of the data by the first transmitter, the first processingunit identifies a failure location on the transmission path.
 3. Theinformation processing apparatus according to claim 2, wherein thepredetermined time period is a time period measured from when theinformation processing apparatus is powered.
 4. The informationprocessing apparatus according to claim 1, wherein the first data isdata that contains information for identification of success oftransmission of the first data; wherein the second data is data thatcontains information for identification of an error.
 5. The informationprocessing apparatus according to claim 1, wherein the secondtransmitter transmits the first data received by the second receiverwithout change.
 6. The information processing apparatus according toclaim 1, wherein, based on receiving the transmitted first data by thefirst receiver, the first processing unit identifies that there is nofailure on the transmission path of the data.
 7. The informationprocessing apparatus according to claim 1, further comprising: a displayconfigured to display the failure location identified by the firstprocessing unit.
 8. The information processing apparatus according toclaim 1, wherein the second data contains an ID of the second processingunit.
 9. The information processing apparatus according to claim 1,further comprising: a scanner configured to scan an image of a document;wherein the second processing unit includes a scan image processorconfigured to perform image processing on image data outputted from thescanner and output the processed image data to the first processingunit.
 10. The information processing apparatus according to claim 1,further comprising: a printer; wherein the second processing unitincludes a print image processor configured to perform image processingon image data outputted from the first processing unit and output theprocessed image data to the printer.
 11. The information processingapparatus according to claim 1, wherein the first processing unit is onechip, and wherein the second processing unit is another one chip that isdifferent from the first processing unit.
 12. The information processingapparatus according to claim 1, wherein the second data contains anumber of processing units which said another data has passed through.13. The information processing apparatus according to claim 1, wherein,based on not receiving the first data by the first receiver, the firstprocessing unit determines that there is a failure on the transmissionpath of the data from the second transmitter to the first receiver. 14.The information processing apparatus according to claim 1, wherein,based on receiving the second data and not receiving the first data bythe first receiver, the first processing unit determines that there is afailure on the transmission path of the data from the first transmitterto the second receiver.
 15. The information processing apparatusaccording to claim 1, wherein the second transmitter transmits thesecond data without receiving the first data.
 16. The informationprocessing apparatus according to claim 1, where the second data is adata indicating the second receiver has not received the first data. 17.The information processing apparatus according to claim 1, furthercomprising: a third processing unit including a third receiverconfigured to receive the first data and the second data transmitted bythe second transmitter and a third transmitter configured to transmitthe first data and the second data transmitted from the secondtransmitter to the first receiver, wherein the second transmittertransmits the first data and the second data to the third receiver. 18.The information processing apparatus according to claim 17, wherein thefirst processing unit, the second processing unit and the thirdprocessing unit are connected in a ring bus.
 19. A method forcontrolling an information processing apparatus comprising a firstprocessing unit including a first transmitter and a first receiver and asecond processing unit including a second receiver and a secondtransmitter, the method comprising: transmitting first data from thefirst transmitter on a basis of powering the information processingapparatus; receiving, using the first receiver, data transmitted fromthe second processing unit; receiving, using the second receiver, thefirst data transmitted by the first transmitter and transmitting, usingthe second transmitter, the first data transmitted from the firsttransmitter and second data to the first receiver; wherein the seconddata is data which is to be transmitted in a situation that the secondreceiver has not received the first data transmitted from the firsttransmitter since the information processing apparatus was powered; andwherein, based on whether or not the first receiver received the firstdata transmitted by the second transmitter and whether or not the firstreceiver received the second data transmitted by the second transmitter,the first processing unit identifies failure location on a transmissionpath of the first data and the data, wherein the first processing unitand the second processing unit are connected in a ring bus.
 20. Themethod according to claim 19, wherein the information processingapparatus further comprises a third processing unit including a thirdreceiver and a third transmitter, receiving, using the third receiver,the first data and the second data transmitted by the secondtransmitter; transmitting, using the third processing unit, the firstdata and the second data transmitted from the second transmitter to thefirst receiver, wherein the first data and the second data istransmitted to the third receiver using the second transmitter.
 21. Themethod according to claim 20, wherein the first processing unit, thesecond processing unit and the third processing unit are connected in aring bus.